Add Subtract, generalized binary operations

2 files changed, 47 insertions, 3 deletions

diff --git a/asm/intel64/encode.cpp b/asm/intel64/encode.cpp
index 6118743..d3bfd91 100644
--- a/asm/intel64/encode.cpp
+++ b/asm/intel64/encode.cpp
@@ -83,6 +83,33 @@ std::shared_ptr<Op> makeAddValue(const FlowGraph::Data& data, const FlowGraph::G
   throw std::runtime_error("ICE: Unsupported type for operand data at add: "s + demangle(typeid(data_storage)));
 }
 
+std::shared_ptr<Op> makeSubValue(const FlowGraph::Data& data, const FlowGraph::Graph& graph)
+{
+ if (data.type() != FlowGraph::DataType::Int) {
+  throw std::runtime_error("Bad type for operand: "s + std::to_string(int(data.type())));
+ }
+
+ if (!data.storage())
+  throw std::runtime_error("ICE: Operand storage is 0");
+
+ auto& data_storage{*data.storage()};
+ if (typeid(data_storage) == typeid(FlowGraph::Constant)) {
+  FlowGraph::Constant& value {dynamic_cast<FlowGraph::Constant&>(data_storage)};
+  if (value.value().size() < sizeof(uint32_t))
+   throw std::runtime_error("ICE: Int data from operand needs at least 4 bytes, got "s + std::to_string(value.value().size()));
+
+  uint32_t immediate = endian::from_little32(value.value());
+
+  return makeOp("sub", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Immediate32(immediate)}});
+ } else if (typeid(data_storage) == typeid(FlowGraph::TemporaryStorage)) {
+  //FlowGraph::TemporaryStorage& storage {dynamic_cast<FlowGraph::TemporaryStorage&>(data_storage)};
+
+  index_t index { graph.scope()->indexOfData(data)};
+  return makeOp("sub", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Mem32Ptr64("rbp", int32_t(index + 1) * -4)}});
+ } else
+  throw std::runtime_error("ICE: Unsupported type for operand data at sub: "s + demangle(typeid(data_storage)));
+}
+
 std::vector<std::shared_ptr<Chunk>> makeMulValue(const FlowGraph::Data& data, const FlowGraph::Graph& graph)
 {
  if (data.type() != FlowGraph::DataType::Int) {
@@ -192,6 +219,10 @@ void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment)
      segment.push_back(makeLoadValue(operands[1], graph));
      segment.push_back(makeAddValue(operands[2], graph));
      segment.push_back(makeStoreValue(operands[0], graph));
+    } else if (op.type() == FlowGraph::BinaryOperationType::Subtract) {
+     segment.push_back(makeLoadValue(operands[1], graph));
+     segment.push_back(makeSubValue(operands[2], graph));
+     segment.push_back(makeStoreValue(operands[0], graph));
     } else if (op.type() == FlowGraph::BinaryOperationType::Multiply) {
      segment.push_back(makeLoadValue(operands[1], graph));
      segment.append(makeMulValue(operands[2], graph));
diff --git a/asm/intel64/sub.cpp b/asm/intel64/sub.cpp
index 2447c15..9efc644 100644
--- a/asm/intel64/sub.cpp
+++ b/asm/intel64/sub.cpp
@@ -14,15 +14,22 @@ Op_sub::Op_sub(const Asm::Args& args)
      args[1].type() == typeid(Asm::Args::Immediate32))
  { // sub eax, imm32 (before "sub reg32, imm32"! It's shorter.)
   machine_code = std::vector<uint8_t>{ 0x2D } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
- } else if (args[0].type() == typeid(Asm::Args::Register32) &&
-     args[1].type() == typeid(Asm::Args::Immediate32))
- { // sub reg32, imm32
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Immediate32)) { // sub reg32, imm32
   machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // sub reg32, [reg64]
+  machine_code = std::vector<uint8_t>{ 0x2B } + ModRM(std::any_cast<Asm::Args::Register32>(args[0]).name(), std::any_cast<Asm::Args::Mem32Ptr64>(args[1]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register16) && args[1].type() == typeid(Asm::Args::Mem16Ptr64)) { // sub reg16, [reg64]
+  machine_code = OpSizePrefix() + std::vector<uint8_t>{ 0x2B } + ModRM(std::any_cast<Asm::Args::Register16>(args[0]).name(), std::any_cast<Asm::Args::Mem16Ptr64>(args[1]).reg());
+
  } else if (args[0].type() == typeid(Asm::Args::Register64) &&
             std::any_cast<Asm::Args::Register64>(args[0]).name() == "rax"  &&
             args[1].type() == typeid(Asm::Args::Immediate32))
  { // sub reg, imm32
   machine_code = REX("W") + machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
  } else {
   throw std::runtime_error("Unimplemented: sub "s + args[0].type().name() + " "s + args[1].type().name());
  }
@@ -36,6 +43,12 @@ bool registered {
                              }) &&
  registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate32>("sub"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
                              return std::make_shared<Op_sub>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register16, Asm::Args::Mem16Ptr64>("sub"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Mem32Ptr64>("sub"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
                              })
 };